For integrated circuits operating at a relatively high supply voltage (e.g., a TTL voltage such as 5 volts), it is advantageous to have an NMOS output pullup driver. The NMOS output driver reduces system power by not pulling the output all the way up to the supply voltage. Integrated circuits operating with a relatively low supply voltage (e.g., 3 volts) typically use CMOS voltage levels and are therefore generally required to pull their outputs up to voltages near the supply. This is usually accomplished using a PMOS pullup transistor.
It is desirable to have a single part that can be programmed using fuses, or some other type of step late in the fabrication process, to configure the part to operate using either 5 volt or 3 volt supply voltages. One implementation may be realized by providing two independent pullup sections. The first pullup would be an NMOS pullup while the second pullup would be a PMOS pullup. The late configuration would configure the appropriate pullup for the desired voltage operation. However, this would require the output section to generally duplicate the pullups which would result in a larger chip.
Implementing a single pullup device for use with both 3 volt and 5 volt input supply voltages may reduce the overall die size. One alternative to such an implementation would be using an NMOS pullup with a boot strapped gate. Another implementation may be a PMOS pullup with an additional circuit to turn off the PMOS pullup after the output has been pulled up to the desired voltage. One way of implementing the PMOS pullup approach is to connect the pullup as a diode for 5 V operation. However, the size of the PMOS pullup is generally (and usually undesirably) determined by the larger 5 volt part rather than the smaller 3 volt part.